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ics9db401c idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 four output differential buffer for pci express datasheet 1 description output features the 9db401c is a db400 version 2.0 yellow cover part with pci express support. it can be used in pc or embedded systems to provide outputs that have low cycle-to-cycle jitter (50ps), low output-to-output skew (100ps), and are pci express gen 1 compliant. the 9db401c supports a 1 to 4 output configuration, taking a spread or non spread differential hcsl input from a ck410(b) main clock such as 954101 and 932s401, or any other differential hcsl pair. 9db401c can generate hcsl or lvds outputs from 50 to 200mhz in pll mode or 0 to 400mhz in bypass mode. there are two de-jittering modes available selectable through the high_bw# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. the src_stop#, pd#, and oe real-time input pins provide completely programmable power management control. ? 4 - 0.7v hcsl or lvds differential output pairs supports zero delay buffer mode and fanout mode bandwidth programming available funtional block diagram key specifications outputs cycle-cycle jitter: < 50ps outputs skew: < 50ps extended frequency range in bypass mode: revision b: up to 333.33mhz revision c: up to 400mhz real-time pll lock detect output pin 28-pin ssop/tssop package available in rohs compliant packaging features/benefits spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread supports undriven differential outputs in pd# and src_stop# modes for power management. stop logic src_in src_in# dif(3:0)) control logic bypass#/pll s data sclk pd spread compatible pll 4 iref oe(3:0) 4 m u x note: polarities shown for oe_inv = 0.
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 2 pin configuration 28-pin ssop & tssop vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 4 25 oe_inv vdd 5 24 vdd dif_1 6 23 dif_6 dif_1# 7 22 dif_6# oe_1 821 oe_6 dif_2 9 20 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#/pll 12 17 high_bw# sclk 13 16 src_stop# sdata 14 15 pd# oe_inv = 0 ics9db401 (same as ics9db104) vdd 1 28 vdda src_in 2 27 gnda src_in# 3 26 iref gnd 425 oe_inv vdd 524vdd dif_1 623 dif_6 dif_1# 722 dif_6# oe1# 821 oe6# dif_2 920 dif_5 dif_2# 10 19 dif_5# vdd 11 18 vdd bypass#/pll 12 17 high_bw# sclk 13 16 src_stop sdata 14 15 pd oe_inv = 1 ics9db401 power groups vdd gnd 1 4 src_in/src_in# 5,11,18, 24 4 dif(1,2,5,6) n/a 27 iref 28 27 analog vdd & gnd for pll core description pin number polarity inversion pin list table 01 8 oe_1 oe1# 15 pd# pd 16 dif_stop# dif_stop 21 oe_6 oe6# pins oe_inv
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 3 pin description for oe_inv = 0 pin # pin name pin type description 1 vdd pwr power supply, nominal 3.3v 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary input 4 gnd pwr ground pin. 5 vdd pwr power supply, nominal 3.3v 6 dif_1 out 0.7v differential true clock output 7 dif_1# out 0.7v differential complement clock output 8oe_1 in active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 9 dif_2 out 0.7v differential true clock output 10 dif_2# out 0.7v differential complement clock output 11 vdd pwr power supply, nominal 3.3v 12 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 5v tolerant. 15 pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal are stopped. 16 src_stop# in active low input to stop src outputs. 17 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 18 vdd pwr power supply, nominal 3.3v 19 dif_5# out 0.7v differential complement clock output 20 dif_5 out 0.7v differential true clock output 21 oe_6 in active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs 22 dif_6# out 0.7v differential complement clock output 23 dif_6 out 0.7v differential true clock output 24 vdd pwr power supply, nominal 3.3v 25 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 26 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core.
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 4 pin description for oe_inv = 1 pin # pin name pin type description 1 vdd pwr power supply, nominal 3.3v 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary input 4 gnd pwr ground pin. 5 vdd pwr power supply, nominal 3.3v 6 dif_1 out 0.7v differential true clock output 7 dif_1# out 0.7v differential complement clock output 8oe1# in active low input for enabling dif pair 1. 1 = tri-state outputs, 0 = enable outputs 9 dif_2 out 0.7v differential true clock output 10 dif_2# out 0.7v differential complement clock output 11 vdd pwr power supply, nominal 3.3v 12 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 13 sclk in clock pin of smbus circuitry, 5v tolerant. 14 sdata i/o data pin for smbus circuitry, 5v tolerant. 15 pd in asynchronous active high input pin used to power down the device. the internal clocks are disabled and the vco is stopped. 16 src_stop in active high input to stop src outputs. 17 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 18 vdd pwr power supply, nominal 3.3v 19 dif_5# out 0.7v differential complement clock output 20 dif_5 out 0.7v differential true clock output 21 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 22 dif_6# out 0.7v differential complement clock output 23 dif_6 out 0.7v differential true clock output 24 vdd pwr power supply, nominal 3.3v 25 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 26 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core.
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 5 absolute max electrical characteristics - input/supply/common output parameters symbol parameter min max units vdd_a 3.3v core supply voltage 4.6 v vdd_in 3.3v logic supply voltage 4.6 v v il input low voltage gnd-0.5 v v ih input high voltage v dd +0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3 v +/-5% gnd - 0.3 0.8 v input high current i ih v in = v dd -5 5 ua i il1 v in = 0 v; inputs with no pull- up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua i dd3.3pll 175 200 ma i dd3.3b y pass 160 175 ma all diff pairs driven 40 ma all differential pairs tri-stated 4 ma input frequency f ipll pll mode 50 200 mhz input frequency f ibypass bypass mode (revision b/rev id = 1h) 0 333.33 mhz input frequency f ibypass bypass mode (revision c/rev id = 2h) 0400mhz pin inductance 1 l p in 7nh1 c in logic inputs 1.5 4 pf 1 c ou t output pin capacitance 4 pf 1 pll bandwidth when pll_bw=0 2.4 3 3.4 mhz 1 pll bandwidth when pll_bw=1 0.7 1 1.4 mhz 1 clk stabilization 1,2 t stab from v dd power-up and after input clock stabilization or de- assertion of pd# to 1st clock 0.5 1 ms 1,2 modulation frequency fmod triangular modulation 30 33 khz 1 tdrive_src_stop# dif output enable after src_sto p # de-assertion 10 15 ns 1,3 tdrive_pd# dif output enable after pd# de-assertion 300 us 1,3 tfall fall time of pd# and src_stop# 5ns1 trise rise time of pd# and src_stop# 5ns2 1 guaranteed by design and characterization, not 100% tested in production. 2 see timin g dia g rams for timin g re q uirements. i dd3.3pd 3 time from deassertion until out p uts are >200 mv input capacitance 1 input low current powerdown current pll bandwidth bw operating supply current full active, c l = full load;
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 6 electrical characteristics - dif 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , ref = 475 ? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max volta g e vovs 1150 1 min volta g e vuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values 0 pp m1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 50 ps 1 pll mode, measurement from differential wavefrom 50 ps 1 bypass mode as additive jitter 50 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 2 all long term accuracy and clock period specifications are guaranteed with the assumption that the input clock complies with ck409/ck410 accuracy requirements jitter, cycle to cycle t jcyc-cyc statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv electrical characteristics - clock input parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min max units notes differential input high voltage v ihdif differential inputs (single-ended measurement) 600 1150 mv 1 differential input low voltage v ildif differential inputs (single-ended measurement) v ss - 300 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input src jitter - cycle to cycle srcj c2cin differential measurement 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 7 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2 figure 1 down device routing. rs rs rt rt hscl output buffer pci ex board down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 1 figure 2 pci express connector routing. rs rs rt rt hscl output buffer pci ex add in board ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 2
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 8 alternative termination for lvds and other common differential signals. figure 3. vdiff vp-p vcm r1 r2 r3 r4 note 0.45 v 0.22v 1.08 33 150 100 100 0.58 0.28 0.3 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 cable connected ac coupled application, figure 4 component value note r5a,r5b 5% r6a,r6b cc 0.1 0.350 vcm volts figure_3. r1b r1a r2a r2b hscl output buffer down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? r3 r4 figure_4. pcie device ref_clk input l4 l4? r6b r5b r6a r5a 3.3 volts cc cc 8.2k 5% uf 1k
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 9 general smbus serial interface information for the ics9db401c how to write: ? controller (host) sends a start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address dd (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 10 smbus table: frequency select register, read/write address (dc/dd) pin # name control function t yp e0 1 pwd bit 7 pd_mode pd# drive mode rw driven hi-z 0 bit 6 stop_mode src_stop# drive mode rw driven hi-z 0 bit 5 pd_src_inv power down and src invert rw normal invert 0 bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 pll_bw# select pll bw rw hi g h bw low bw 1 bit 1 bypass# bypass#/pll rw fan-out zdb 1 bit 0 src_div# src divide by 2 select rw x/2 1x 1 smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 reserved reserved rw x bit 6 dif_6 output control rw disable enable 1 bit 5 dif_5 output control rw disable enable 1 bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 dif_2 output control rw disable enable 1 bit 1 dif_1 output control rw disable enable 1 bit 0 reserved reserved rw x smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 reserved reserved rw x bit 6 dif_6 output control rw free-run stoppable 0 bit 5 dif_5 output control rw free-run stoppable 0 bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 dif_2 output control rw free-run stoppable 0 bit 1 dif_1 output control rw free-run stoppable 0 bit 0 reserved reserved rw x smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 6,7 - b y te 3 19,20 - - 9,10 - b y te 2 - 22,23 - - 9,10 6,7 b y te 1 - 22,23 19,20 - - -reserved - - -reserved b y te 0 - - reserved reserved reserved reserved reserved reserved reserved reserved
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 11 smbus table: vendor & revision id register pin # name control function t yp e0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e0 1 pwd bit 7 rw 0 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 1 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 device id 3 reserved device id 0 reserved device id 2 reserved device id 1 reserved device id 5 reserved device id 4 reserved device id 6 reserved device id 7 (msb) reserved byte 6 - writing to this register configures how many bytes will be read back. - - - - - - - b y te 5 - - - - - vendor id - - - - - - - b y te 4 - revision id - - -
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 12 the pd# pin cleanly shuts off all clocks and places the device into a power saving mode. pd# must be asserted before shutting off the input clock or power to insure an orderly shutdown. pd is asynchronous active-low input for both powering down the device and powering up the device. when pd# is asserted, all clocks will be driven high, or tri-stated (depending on the pd# drive mode and output control bits) before the pll is shut down. pd# when pd# is sampled low by two consecutive rising edges of dif#, all dif outputs must be held high, or tri-stated (depending on the pd# drive mode and output control bits) on the next high-low transition of the dif# outputs. when the pd# drive mode bit is set to ?0?, all clock outputs will be held with dif driven high with 2 x i ref and dif# tri-stated. if the pd# drive mode bit is set to ?1?, both dif and dif# are tri-stated. pd# assertion power-up latency is less than 1 ms. this is the time from de-assertion of the pd# pin, or vdd reaching 3.3v, or the time from valid src_in clocks until the time that stable clocks are output from the device (pll locked). if the pd# drive mode bit is se t to ?1?, all the dif outputs must driven to a voltage of >200 mv within 300 ms of pd# de-assertion. pd# de-assertion pwrdwn# dif dif# pwrdwn# dif dif# tstable <1ms tdrive_pwrdwn# <300us, >200mv
ics9db401c four output differential buffer for pci express 13 asserting src_stop# causes all dif outputs to stop after their next transition (if the control register settings allow the outp ut to stop). when the src_stop# drive bit is ?0?, the final state of all stopped dif outputs is dif = high and dif# = low. ther e is no change in output drive current. dif is driven with 6xi ref. dif# is not driven, but pulled low by the termination. when the src_stop# drive bit is ?1?, the final state of all dif output pins is low. both dif and dif# are not driven. src_stop# - assertion (transition from '1' to '0') all stopped differential outputs resume normal operation in a glitch-free manner. the de-assertion latency to active outputs i s 2-6 dif clock periods, with all dif outputs resuming simultaneously. if the src_stop# drive control bit is ?1? (tri-state), al l stopped dif outputs must be driven high (>200 mv) within 10 ns of de-assertion. the src_stop# signal is an active-low asynchronous input that cleanly stops and starts the dif outputs. a valid clock must be present on src_in for this input to work properly. the src_stop# signal is de-bounced and must remain stable for two consecutive rising edges of dif# to be recognized as a valid assertion or de-assertion. src_stop# pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_1 (src_stop = driven, pd = driven) src_stop_2 (src_stop =tristate, pd = driven) note: polarities in timing diagrams are shown oe_inv = 0. they are similar to oe_inv = 1.
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 14 pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_4 (src_stop = tristate, pd = tristate) src_stop_3 (src_stop = driven, pd = tristate)
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 15 min max min max a--2.00 --.079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 v ariations min max min max 28 9.90 10.50 .390 .413 10-0033 209 mil ssop symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.65 basic 0.0256 basic reference doc.: jedec publication 95, mo-150 see variations see variations n d mm. d (inch) seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e ordering information ics9db401cflft example: designation for tape and reel packaging rohs compliant (optional) package type f = ssop revision designator device type (consists of 3 to 7 digit numbers) prefix ics = standard device ics xxxx c f lf t
idt tm /ics tm four output differential buffer for pci express ics9db401c rev e 03/18/08 ics9db401c four output differential buffer for pci express 16 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.190.30.007.012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.450.75.018.030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) ordering information ICS9DB401CGLFT example: designation for tape and reel packaging rohs compliant (optional) package type g = tssop revision designator device type (consists of 3 to 7 digit numbers) prefix ics = standard device ics xxxx c g lf t
ics9db401c four output differential buffer for pci express 17 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 4/21/2005 changed ordering information from"ln" to "lf". 14,15 a 8/15/2005 1. updated lf ordering information to rohs compliant. 2. release to web. 14-15 b 9/7/2006 updated electrical characteristics. various c 5/22/2007 updated polarity inversion table. 2 d 2/28/2008 added input clock specs 6 e 3/18/2008 fixed typo in clock input parameters 6

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